Storage devices typically have a storage controller and a nonvolatile storage medium that can be accessed randomly. Such a storage medium is, for example, a disk array with a number of hard disk drives (HDDs) or nonvolatile semiconductor memory drives (SSDs). The storage controller has a front-end interface (hereinafter abbreviated as FE I/F) for connection to a host system, a back-end interface (hereinafter abbreviated as BE I/F) for connection to the disk array, cache memory (hereinafter abbreviated as CM) for temporarily storing data that is read from or written to the disk array by the host system, and its interface (hereinafter, CM I/F). The storage controller also has a processor for controlling data transfer between the host system and CM I/F and between the disk array and CM I/F.
As a communication network standard specification for connecting the processor to the EF I/F, BE I/F, and the like, there is known “PCI Express.” Meanwhile, as an extended standard of the PCI Express, there is also known “Multi-Root I/O Virtualization and Sharing Specification” (hereinafter, “MR-IOV”) that is the standard to enable sharing of an I/O device among a plurality of processors. For example, Patent Literature 1 discloses a technique related to a communication network that uses the MR-IOV. As the MR-IOV is the standard specification, it is considered that components such as switches that comply with the MR-IOV can be commoditized. That is, it is expected that constructing the internal network of a storage controller using the MR-IOV that is the standard specification allow cost reduction of the storage controller.
In the MR-IOV, a communication network includes, for example, a plurality of root complexes (hereinafter, “RCs”), to each of which is connected a processor, a plurality of root ports (hereinafter, “RPs”) provided in the RCs, a plurality of endpoints (hereinafter, “EPs”) that serve as the base points for data input/output, and a plurality of switches for connecting the RPs and EPs. Each EP is configured to be capable of, when accessed from a processor via an RP, providing its function (a data transfer function with which input data is transferred to another device, for example) to the processor (so that the processor can control data transfer on the each EP). With such a configuration, a plurality of processors can share each EP and can independently access each EP via an RP (each processor can independently control data transfer on each EP). Accordingly, the plurality of processors can independently perform data transfer operations without the need of increasing the number of EPs, whereby the performance of the data transfer processing can be improved.
When focus is placed on a single RP in the MR-IOV, a tree-like topology that has the RP, and EPs and switch logically connected to the RP, is referred to as a “virtual hierarchy” (hereinafter, “VH”). In a communication network that complies with the MR-IOV (hereinafter, “MR-IOV network”), VHs exist in the same number as a plurality of RPs that reside in the MR-IOV network. A single VH represents an address space used for data transfer controlled by a processor for each RP. Assume, for example, that there exist the first VH that has an RP1, EP1, and EP2 and the second VH that has an RP2, EP1, and EP2 in the MR-IOV network. It is also assumed that the RP1 is provided in an RC1 connected to a processor 1, and the RP2 is provided in a RC2 connected to a processor 2. In such a case, the processor 1 and processor 2 can independently control data transfer from the EP1 to the EP2 (or in the reverse direction) via the RP1 on the first VH and via the RP2 on the second VH, respectively.